ARM > Introduction to ARM > Single Register Data Transfer

by David Thomas on

Single Register Data Transfer

<operation>{cond}{size} Rd, <address>


  • LDR
    • Rd := value at <address>
  • STR
    • value at <address> := Rd

{size} is specified to transfer bytes or half-words:

  • <operation>B
    • unsigned byte
  • <operation>SB
    • signed byte
  • <operation>H
    • unsigned half-word
  • <operation>SH
    • signed half-word

Examples of Single Register Data Transfer

  • LDR r0,[r1]
    • Load word addressed by R1 into R0.
  • LDRB r0,[r1]
    • The same as above but loads a byte.


The instructions for accessing half-words were a later addition to the instruction set so have some restrictions (described on the next page).

SB and SH modes are not available with STR.

Alignment Restrictions

In general, values loaded from or stored to memory must be aligned to the size of the data type:

  • 32-bit words must be 4-byte aligned.
  • 16-bit half-words must be 2-byte aligned.
  • Bytes – no restriction.

This restriction was relaxed in ARMv6.


Values can only be loaded from, or stored to, memory at a multiple of that type size. For example, a half-word can only be loaded from even addresses. (doubles are an exception and can live on 4-byte boundaries in some architecture versions).