ARM > Introduction to ARM > Single Register Data Transfer
Examples of Single Register Data Transfer
LDR r0,[r1]
- Load word addressed by R1 into R0.
LDRB r0,[r1]
- The same as above but loads a byte.
Remarks
The instructions for accessing half-words were a later addition to the instruction set so have some restrictions (described on the next page).
SB
and SH
modes are not available with STR
.
Remarks
Values can only be loaded from, or stored to, memory at a multiple of that type size. For example, a half-word can only be loaded from even addresses. (double
s are an exception and can live on 4-byte boundaries in some architecture versions).