ARM > Introduction to ARM > Multiple Register Data Transfer
Examples of Multiple Register Data Transfer Instructions
LDMIA r0, {r3,r7}
- Load words addressed by R0 into R3 and R7.
- Increment After each load.
LDMIA r0, {r3-r7}
- Load words addressed by R0 into R3, R4, R5, R6 and R7.
- Increment After each load.
STMDB r1!, {r6-r8}
- Store R6,R7,R8 into words addressed by R1.
- Write back the final address into R1.
- Decrement Before each store.
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